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| M36W108T M36W108B 8 Mbit (1Mb x8, Boot Block) Flash Memory and 1 Mbit (128Kb x8) SRAM Low Voltage Multi-Memory Product NOT FOR NEW DESIGN s M36W108T and M36W108B are replaced respectively by the M36W108AT and M36W108AB SUPPLY VOLTAGE - VCCF = VCCS = 2.7V to 3.6V: for Program, Erase and Read s BGA LGA s s ACCESS TIME: 100ns LOW POWER CONSUMPTION - Read: 40mA max. (SRAM chip) - Stand-by: 30A max. (SRAM chip) - Read: 10mA max. (Flash chip) - Stand-by: 100A max. (Flash chip) LBGA48 (ZM) 6 x 8 solder balls LGA48 (ZN) 6 x 8 solder lands FLASH MEMORY s 8 Mbit (1Mb x 8) BOOT BLOCK ERASE s s Figure 1. Logic Diagram PROGRAMMING TIME: 10s typical PROGRAM/ERASE CONTROLLER (P/E.C.) - Program Byte-by-Byte - Status Register bits and Ready/Busy Output VCCF VCCS s MEMORY BLOCKS - Boot Block (Top or Bottom location) - Parameter and Main Blocks A0-A19 W EF G RP E1S E2S M36W108T M36W108B RB 20 8 DQ0-DQ7 s s BLOCK, MULTI-BLOCK and CHIP ERASE ERASE SUSPEND and RESUME MODES - Read and Program another Block during Erase Suspend s 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code, M36W108T: D2h - Device Code, M36W108B: DCh s SRAM s 1 Mbit (128Kb x 8) s VSS AI02509 POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS LOW VCC DATA RETENTION: 2V 1/35 s May 1999 This is information on a product still in production but not recommended for new designs. M36W108T, M36W108B Figure 2. LBGA and LGA Connections (Top View) 1 2 3 4 5 6 A W A14 A11 G A10 E1S B VCCS A18 A8 DQ7 DQ5 VSS C A17 NC A5 DQ4 DQ2 DQ1 D VSS EF NC DQ0 A0 A1 E NC NC DQ3 A6 A3 A2 F NC VCCF NC A19 A7 A4 G NC DQ6 A13 RP RB E2S H NC A12 NC A16 A15 A9 AI02508 Table 1. Signal Names A0-A16 A17-A19 DQ0-DQ7 EF E1S, E2S G W RP RB VCCF VCCS VSS Address Inputs Address Inputs for Flash Chip Data Input/Outputs, Command Inputs for Flash Chip Chip Enable for Flash Chip Chip Enable for SRAM Chip Output Enable Write Enable Reset for Flash Chip Ready/Busy Output for Flash Chip Supply Voltage for Flash Chip Supply Voltage for SRAM Chip Ground DESCRIPTION The M36W108 is multi-chip device containing an 8 Mbit boot block Flash memory and a 1 Mbit of SRAM. The device is offered in the new Chip Scale Package solutions: LBGA48 1.0 mm ball pitch and LGA48 1.0 mm land pitch. The two components, of the package's overall 9 Mbit of memory, are distinguishable by use of the three chip enable lines: EF for the Flash memory, E1S and E2S for the SRAM. The Flash memory component is identical with the M29W008 device. It is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byte basis using only a single 2.7V to 3.6V V CCF supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. Instructions for Read/Reset, Auto Select for reading the Electronic Signature, Programming, Block 2/35 M36W108T, M36W108B Table 2. Absolute Maximum Ratings (1) Symbol TA TBIAS TSTG VIO (2) VCCF VCCS V(EF, RP) PD Parameter Ambient Operating Temperature (3) Temperature Under Bias Storage Temperature Input or Output Voltage Flash Chip Supply Voltage SRAM Chip Supply Voltage EF, RP Voltage Power Dissipation Value -40 to 85 -50 to 125 -65 to 150 -0.5 to VCC +0.5 -0.6 to 5 -0.3 to 4.6 0.6 to 13.5 0.7 Unit C C C V V V V W Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns. 3. Depends on range. and Chip Erase, Erase Suspend and Resume are written to the device in cycles of commands to a Command Interface using standard microprocessor write timings. The SRAM component is a low power SRAM that features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7V to 3.6V V CCS supply, and all inputs and outputs are TTL compatible. SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A16). Addresses A0 to A16 are common inputs for the Flash chip and the SRAM chip. The address inputs for the Flash memory or the SRAM array are latched during a write operation on the falling edge of Flash Chip Enable (EF), SRAM Chip Enable (E1S or E2S) or Write Enable (W). Address Inputs (A17-A19). Address A17 to A19 are address inputs for the Flash chip. They are latched during a write operation on the falling edge of Flash Chip Enable (EF) or Write Enable (W). Data Input/Outputs (DQ0-DQ7). The input is data to be programmed in the Flash or SRAM memory array or a command to be written to the C.I. of the Flash chip. Both are latched on the rising edge of Flash Chip Enable (EF), SRAM Chip Enable (E1S or E2S) or Write Enable (W). The output is data from the Flash memory or SRAM array, the Electronic Signature Manufacturer or Device codes or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Flash Chip Enable (EF) or SRAM Chip Enable (E1S or E2S) and Output Enable (G) are active. The output is high impedance when the both the Flash chip and the SRAM chip are deselected or the outputs are disabled and when Reset (RP) is at a V IL. Flash Chip Enable (EF). The Chip Enable input for Flash activates the memory control logic, input buffers, decoders and sense amplifiers. EF at VIH deselects the memory and reduces the power consumption to the standby level. EF can also be used to control writing to the command register and to the Flash memory array, while W remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at V IH at the same time. SRAM Chip Enable (E1S, E2S). The Chip Enable inputs for SRAM activate the memory control logic, input buffers, decoders and sense amplifiers. E1S at VIH or E2S at VIL deselects the memory and reduces the power consumption to the standby level. E1S and E2S can also be used to control writing to the SRAM memory array, while W remains at VIL. It is not allowed to set EF at VIL, E1S at VIL and E2S at VIH at the same time. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When G is High the outputs are High impedance. Write Enable (W). The Write Enable input controls writing to the Command Register of the Flash chip and Address/Data latches. 3/35 M36W108T, M36W108B Table 3. Main Operation Modes (1) Operation Mode Flash Chip Read VIL SRAM Chip Read Flash Chip Write VIL SRAM Chip Write Flash Chip Output Disable X SRAM Chip Output Disable Flash Chip Stand-by Flash Chip Reset X X SRAM Chip Stand-by X Note: 1. X = VIL or VIH. EF VIL E1S VIH X VIL VIH X VIL VIH X VIL X VIH X VIH X E2S X VIL VIH X VIL VIH X VIL VIH X X VIL X VIL G VIL VIL VIL VIH VIH X VIH VIH VIH X X X X X W VIH VIH VIH VIL VIL VIL VIH VIH VIH X X X X X RP VIH VIH X VIH VIH X X X X VIH VIL VIL VIL VIL DQ0-DQ7 Data Output Data Output Data Output Data Input Data Input Data Input Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z VIH VIL VIH X VIH VIH X Reset Input (RP). The Reset input provides hardware reset of the Flash chip. Reset of the Flash memory is achieved by pulling RP to VIL for at least t PLPX. When the reset pulse is given, if the Flash memory is in Read or Standby modes, it will be available for new operations in tPHEL after the rising edge of RP. If the Flash memory is in Erase or Program mode the reset will take tPLYH during which the Ready/ Busy (RB) signal will be held at VIL. The end of the Flash memory reset will be indicated by the rising edge of RB. A hardware reset during an Erase or Program operation will corrupt the data being programmed or the block(s) being erased. See Table 17 and Figure 9. Ready/Busy Output (RB). Ready/Busy is an open-drain output of the Flash chip. It gives the internal state of the Program/Erase Controller (P/ E.C.) of the Flash device. When RB is Low, the Flash device is busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase Suspend instruction. When RB is High, the Flash device is ready for any Read, Program or Erase operation. The RB will also be High when the Flash memory is put in Erase Suspend or Standby modes. VCCF Supply Voltage. Flash memory power supply for all operations (Read, Program and Erase). VCCS Supply Voltage. SRAM power supply for all operations (Read, Program). VSS Ground. VSS is the reference for all voltage measurements. POWER SUPPLY Power Up. The Flash memory Command Interface is reset on power up to Read Array. Either Flash Chip Enable (EF) or Write Enable (W) inputs must be tied to VIH during Power Up to allow maximum security and the possibility to write a command on the first rising edge of EF and W. Any write cycle initiation is blocked when VCCF is below VLKO. Supply Rails. Normal precautions must be taken for supply voltage decoupling; each device in a system should have the V CCF, VCCS rails decoupled with a 0.1F capacitor close to the V CCF, VCCS and V SS pins. The PCB trace widths should be sufficient to carry the V CCF and V CCS program currents and the V CCF erase current required. 4/35 M36W108T, M36W108B Figure 3. Internal Functional Arrangement VCCF VSS RP EF A0-A19 8 Mbit Flash Memory (1Mb x 8) RB DQ0-DQ7 W G VCCS VSS A0-A16 1 Mbit SRAM (128 Kb x 8) E1S E2S AI02444 5/35 M36W108T, M36W108B FLASH MEMORY COMPONENT Organization and Architecture Organization. The Flash chip is organized as 1Mbit x 8. The memory uses the address inputs A0-A19 and the Data Input/Outputs DQ0-DQ7. Memory control is provided by Chip Enable (EF), Output Enable (G) and Write Enable (W) inputs. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, while Status Register data outputs on DQ6 and DQ2 provide Toggle signals to indicate the state of the P/E.C. operations. A Ready/Busy (RB) output indicates the completion of the internal algorithms. Memory Blocks. The device features asymmetrically blocked architecture providing system memory integration. Both Top and Bottom Boot Block devices have an array of 19 blocks, one Boot Block of 16K Bytes, two Parameter Blocks of 8K Bytes, one Main Block of 32K Bytes and fifteen Main Blocks of 64K Bytes. The Top Boot Block version has the Boot Block at the top of the memory address space and the Bottom Boot Block version locates the Boot Block starting at the bottom. The memory maps and block address tables are showed in Figures 4, 5 and Tables 4, 5. Each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase operations are managed automatically by the P/E.C. The block erase operation can be suspended in order to read from or program to any block not being erased, and then resumed. Device Operations The following operations can be performed using the appropriate bus cycles: Read Array, Write command, Output Disable, Standby and Reset (see Table 6). Read. Read operations are used to output the contents of the Memory Array, the Electronic Signature or the Status Register. Both Chip Enable (EF) and Output Enable (G) must be low, with Write Enable (W) high, in order to read the output of the memory. Table 5. Bottom Boot Block, Flash Block Address Size (KWord) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 32 8 8 16 Address Range F0000h-FFFFFh E0000h-EFFFFh D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 08000h-0FFFFh 06000h-07FFFh 04000h-05FFFh 00000h-03FFFh Table 4. Top Boot Block, Flash Block Address Size (KWord) 16 8 8 32 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address Range FC000h-FFFFFh FA000h-FBFFFh F8000h-F9FFFh F0000h-F7FFFh E0000h-EFFFFh D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 00000h-0FFFFh 6/35 M36W108T, M36W108B Write. Write operations are used to give Instruction Commands to the memory or to latch input data to be programmed. A write operation is initiated when Chip Enable (EF) is Low and Write Enable (W) is at VIL with Output Enable (G) at VIH. Addresses are latched on the falling edge of W or EF whichever occurs last. Commands and Input Data are latched on the rising edge of W or EF whichever occurs first. Output Disable. The data outputs are high impedance when the Output Enable (G) is at VIH with Write Enable (W) at VIH. Standby. The memory is in standby when Chip Enable (EF) is at V IH and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable (G) or Write Enable (W) inputs. Automatic Standby. After 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumption is reduced to the CMOS standby value, while outputs still drive the bus. Table 6. Flash User Bus Operations (1) Operation Read Byte Write Byte Output Disable Stand-by Reset Note: 1. X = VIL or VIH. Instructions and Commands Seven instructions are defined (see Table 7) to perform Read Array, Auto Select (to read the Electronic Signature), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Data Polling, Toggle, Error bits and the RB output may be read at any time, during programming or erase, to monitor the progress of the operation. Instructions, made up of commands written in cycles, can be given to the Program/Erase Controller through a Command Interface (C.I.). The C.I. latches commands written to the memory. Commands are made of address and data sequences. Two coded cycles unlock the Command Interface. They are followed by an input command or a confirmation command. The coded sequence consists of writing the data AAh at the address 5555h during the first cycle and the data 55h at the address 2AAAh during the second cycle. EF VIL VIL VIL VIH X G VIL VIH VIH X X W VIH VIL VIH X X RP VIH VIH VIH VIH VIL A0 A0 A0 X X X A1 A1 A1 X X X A6 A6 A6 X X X A9 A9 A9 X X X A12 A12 A12 X X X A15 A15 A15 X X X DQ0-DQ7 Data Output Data Input Hi-Z Hi-Z Hi-Z Table 7. Read Flash Electronic Signature Code Manufact. Code M36W108T Device Code M36W108B VIL VIL VIH VIH VIL Don't care DCh Device EF VIL VIL G VIL VIL W VIH VIH A0 VIL VIH A1 VIL VIL Other Addresses Don't care Don't care DQ0-DQ7 20h D2h 7/35 M36W108T, M36W108B Table 8. Flash Commands Hex Code 00h 10h 20h 30h 80h 90h A0h B0h F0h Command Invalid/Reserved Chip Erase Confirm Reserved Block Erase Resume/Confirm Set-up Erase Read Electronic Signature/ Block Protection Status Program Erase Suspend Read Array/Reset Instructions are composed of up to six cycles. The first two cycles input a Coded Sequence to the Command Interface which is common to all instructions (see Table 9). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data or Electronic Signature for Read operations. In order to give additional data protection, the instructions for Program and Block or Chip Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (block or chip), the fourth and fifth cycles input a further Coded Sequence before the Erase confirm command on the sixth cycle. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. When power is first applied or if V CCF falls below VLKO, the command interface is reset to Read Array. Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosen to assure maximum data security. Read/Reset (RD) Instruction. The Read/Reset instruction consists of one write cycle giving the command F0h. It can be optionally preceded by the two Coded cycles. Subsequent read operations will read the memory array addressed and output the data read. A wait state of tPLYH is necessary after Read/Reset prior to any valid read if the memory was in an Erase or Program mode when the RD instruction is given (see Table 17 and Figure 9). Auto Select (AS) Instruction. This instruction uses the two Coded cycles followed by one write cycle giving the command 90h to address 5555h for command set-up. A subsequent read will output the Manufacturer Code or the Device Code (Electronic Signature) depending on the levels of A0 and A1 (see Table 7). The Electronic Signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the Flash memory. The Manufacturer Code, 20h, is output when the addresses lines A0 and A1 are at VIL, the Device Code is output when A0 is at VIH with A1 at VIL. Other address inputs are ignored. Program (PG) Instruction. This instruction uses four write cycles. The Program command A0h is written to address 5555h on the third cycle after two Coded Cycles. A fourth write operation latches the Address and the Data to be written and starts the P/E.C. Read operations output the Status Register bits after the programming has started. Memory programming is made only by writing '0' in place of '1'. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows verification of any possible error. Programming at an address not in blocks being erased is also possible during erase suspend. In this case, DQ2 will toggle at the address being programmed. 8/35 M36W108T, M36W108B Block Erase (BE) Instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address 5555h on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded Cycles. During the input of the second command an address within the block to be erased is given and latched into the memory. Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Coded cycles. The erase will start after the erase timeout period (see Erase Timer Bit DQ3 description). Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is '0' the Block Erase Command has been given and the timeout is running, if DQ3 is '1', the timeout has expired and the P/E.C. is erasing the block(s). If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before to erasing to FFh. Read operations after the sixth rising edge of W or EF output the Status Register bits. During the execution of the erase by the P/E.C., the memory only accepts the Erase Suspend (ES) and Read/Reset (RD) instructions. A Read/Reset command will definitively abort erasure and result in invalid data in blocks being erased. A complete state of the block erase operation is given by the Status Register bits (see DQ2, DQ3, DQ5, DQ6 and DQ7 description). Chip Erase (CE) Instruction. This instruction uses six write cycles. The Erase Set-up command 80h is written to address 5555h on the third cycle after the two Coded Cycles. The Chip Erase Confirm command 10h is similarly written on the sixth cycle after another two Coded Cycles. If the second command given is not an erase confirm or if the Coded Sequence is wrong, the instruction aborts and the device is reset to Read Array. It is not necessary to program the array with 00h first as the P/E.C. will automatically do this before erasing it to FFh. Read operations after the sixth rising edge of W or EF output the Status Register bits. A complete state of the chip erase operation is given by the Status Register bits (see DQ2, DQ3, DQ5, DQ6 and DQ7 description). Erase Suspend (ES) Instruction. The Block Erase operation may be suspended by this instruction which consists of writing the command B0h without any specific address. No Coded Cycles are required. It permits reading of data from another block and programming in another block while an erase operation is in progress. Erase suspend is accepted only during the Block Erase instruction execution. Writing this command during the erase timeout period will, in addition to suspending the erase, terminate the timeout. The Toggle bit DQ6 stops toggling when the P/E.C. is suspended. The Toggle bits will stop toggling between 0.1s and 15s after the Erase Suspend (ES) command has been written. The device will then automatically be set to Read Memory Array mode. When erase is suspended, a Read from blocks being erased will output DQ2 toggling and DQ6 at '1'. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume (ER) and the Program (PG) instructions. A Program operation can be initiated during Erase Suspend in one of the blocks not being erased. It will result in both DQ2 and DQ6 toggling when the data is being programmed. A Read/Reset command will definitively abort erasure and result in invalid data in the blocks being erased. Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any Coded cycles. 9/35 M36W108T, M36W108B Table 9. Flash Instructions (1) Mne. Instr. Cyc. 1+ Read/Reset RD (2,4) Memory Array 3+ Addr. (3,7) Data Addr. (3,7) Data AS (4) Auto Select 3+ Addr. (3,7) Data Addr. (3,7) PG Program 4 Data Addr. (3,7) Data CE Chip Erase 6 Addr. (3,7) Data Erase ES (10) Suspend Erase Resume 1 Addr. (3,7) Data 1 Addr. (3,7) Data AAh 5555h AAh 5555h AAh X B0h X 30h 55h 2AAAh 55h 2AAAh 55h A0h 5555h 80h 5555h 80h 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. X Read Memory Array until a new write cycle is initiated. F0h 5555h AAh 5555h AAh 5555h 2AAAh 55h 2AAAh 55h 2AAAh 5555h F0h 5555h 90h 5555h Read Memory Array until a new write cycle is initiated. Read Electronic Signature or Block Protection Status until a new write cycle is initiated. See Note 5 and 6. Program Address Read Data Polling or Toggle Bit Program until Program completes. Data 5555h AAh 5555h AAh 2AAAh 55h 2AAAh 55h Block Address 30h 5555h Note 9 10h Additional Block (8) 30h 7th Cyc. BE Block Erase 6 Read until Toggle stops, then read all the data needed from any Block(s) not being erased then Resume Erase. Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time. ER Note: 1. Commands not interpreted in this table will default to read array mode. 2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase, Erase Suspend or Program mode before starting any new operation (see Table 14 and Figure 7). 3. X = Don't care. 4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles. 5. Signature Address bits A0, A1, at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will output Device code. 6. Block Protection Address: A0, at V IL, A1 at VIH and A13-A19 within the Block will output the Block Protection status. 7. For Coded cycles address inputs A15-A19 are don't care. 8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, real Data Polling or Toggle bit until Erase is completed or suspended. 9. Read Data Polling, Toggle bits or RB until Erase completes. 10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. 10/35 M36W108T, M36W108B Table 10. Flash Status Register Bits (1) DQ Name Logic Level `1' `0' 7 Data Polling DQ DQ `-1-0-1-0-1-0-1-' DQ 6 Toggle Bit `-1-1-1-1-1-1-1-' `1' 5 4 Error Bit `0' Reserved `1' 3 Erase Time Bit `0' Erase Timeout Period On-going Chip Erase, Erase or Erase Suspend on the currently addressed block. Erase Error due to the currently addressed block (when DQ5 = `1') Program on-going, Erase on-going on another block or Erase Complete Erase Suspend read on non Erase Suspend block Erase Timeout Period Expired P/E.C. Erase operation has started. Only possible command entry is Erase Suspend (ES). An additional block to be erased in parallel can be entered to the P/E.C. Program or Erase On-going Definition Erase Complete or erase block in Erase Suspend Erase On-going Program Complete or data of non erase block during Erase Suspend Program On-going Erase or Program On-going Program Complete Erase Complete or Erase Suspend on currently addressed block Program or Erase Error Successive reads output complementary data on DQ6 while Programming or Erase operations are on-going. DQ6 remains at constant level when P/E.C. operations are completed or Erase Suspend is acknowledged. This bit is set to `1' in the case of Programming or Erase failure. Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. Note `-1-0-1-0-1-0-1-' 2 Toggle Bit `1' Indicates the erase status and allows to identify the erased block. DQ 1 0 Reserved Reserved Note: 1. Logic level `1' is High, `0' is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. 11/35 M36W108T, M36W108B Table 11. Flash Polling and Toggle Bits (1) Mode Program Erase Erase Suspend Read (in Erase Suspend block) Erase Suspend Read (outside Erase Suspend block) Erase Suspend Program DQ7 DQ7 0 DQ6 Toggle Toggle DQ2 1 Note 1 1 1 Toggle DQ7 DQ6 DQ2 DQ7 Toggle N/A Note: 1. Toggle if the address is within a block being erased. `1' if the address is within a block not being erased. Status Register Bits P/E.C. status is indicated during execution by Data Polling on DQ7, detection of Toggle on DQ6 and DQ2, or Error on DQ5 and Erase Timer DQ3 bits. Any read attempt during Program or Erase command execution will automatically output these five Status Register bits. The P/E.C. automatically sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1 and DQ4) are reserved for future use and should be masked (see Table 10 and Table 11). Data Polling Bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7. During Erase operation, it outputs a '0'. After completion of the operation, DQ7 will output the bit last programmed or a '1' after erasing. Data Polling is valid and only effective during P/E.C. operation, that is after the fourth W pulse for programming or after the sixth W pulse for erase. It must be performed at the address being programmed or at an address within the block being erased. If all the blocks selected for erasure are protected, DQ7 will be set to '0' for about 100s, and then return to the previous addressed memory data value. See Figure 9 for the Data Polling flowchart and Figure 11 for the Data Polling waveforms. DQ7 will also flag the Erase Suspend mode by switching from '0' to '1' at the start of the Erase Suspend. In order to monitor DQ7 in the Erase Suspend mode an address within a block being erased must be provided. For a Read Operation in Erase Suspend mode, DQ7 will output '1' if the read is attempted on a block being erased and the data value on oth- er blocks. During Program operation in Erase Suspend Mode, DQ7 will have the same behaviour as in the normal program execution outside of the suspend mode. Toggle Bit (DQ6). When Programming or Erasing operations are in progress, successive attempts to read DQ6 will output complementary data. DQ6 will toggle following toggling of either G, or EF when G is at VIL. The operation is completed when two successive reads yield the same output data. The next read will output the bit last programmed or a '1' after erasing. The toggle bit DQ6 is valid only during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. If the blocks selected for erasure are protected, DQ6 will toggle for about 100s and then return back to Read. DQ6 will be set to '1' if a Read operation is attempted on an Erase Suspend block. When erase is suspended DQ6 will toggle during programming operations in a block different to the block in Erase Suspend. Either EF or G toggling will cause DQ6 to toggle. See Figure 11 for Toggle Bit flowchart and Figure 15 for Toggle Bit waveforms. Toggle Bit (DQ2). This toggle bit, together with DQ6, can be used to determine the device status during the Erase operations. It can also be used to identify the block being erased. During Erase or Erase Suspend a read from a block being erased will cause DQ2 to toggle. A read from a block not being erased will set DQ2 to '1' during erase and to DQ2 during Erase Suspend. During Chip Erase a read operation will cause DQ2 to toggle as all blocks are being erased. DQ2 will be set to '1' during program operation and when erase is complete. After erase completion and if the error bit DQ5 is set to '1', DQ2 will toggle if the faulty block is addressed. Error Bit (DQ5). This bit is set to '1' by the P/E.C. when there is a failure of programming, block erase, or chip erase that results in invalid data in the memory block. In case of an error in block erase or program, the block in which the error occurred or to which the programmed data belongs, must be discarded. The DQ5 failure condition will also appear if a user tries to program a '1' to a location that is previously programmed to '0'. Other Blocks may still be used. The error bit resets after a Read/Reset (RD) instruction. In case of success of Program or Erase, the error bit will be set to '0'. Erase Timer Bit (DQ3). This bit is set to '0' by the P/E.C. when the last block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the erase timeout period is finished, after 50s to 90s, DQ3 returns to '1'. 12/35 M36W108T, M36W108B Table 12. Flash Program/Erase Times and Endurance (TA = 0 to 70 C; VCC = 2.7 V to 3.6 V) Flash Memory Chip Parameter Min Chip Erase (Preprogrammed) Chip Erase Boot Block Erase Parameter Block Erase Main Block (32Kb) Erase Main Block (64Kb) Erase Chip Program (Byte) Byte Program Program/Erase Cycles (per Block) 100,000 Typ 5 12 2.4 2.3 2.7 3.3 8 10 8 10 15 Typical after 100k W/E Cycles 3.3 Unit Max sec sec sec sec sec sec sec s cycles 13/35 M36W108T, M36W108B SRAM COMPONENT Device Operations The following operations can be performed using the appropriate bus cycles: Read Array, Write Array, Output Disable, Power Down (see Table 13). Read. Read operations are used to output the contents of the SRAM Array. The SRAM is in Read mode whenever Write Enable (W) is at VIH with Output Enable (G) at V IL, and both Chip Enables (E1S and E2S) are asserted. Valid data will be available at the eight output pins within t AVQV after the last stable address, providing G is Low, E1S is Low and E2S is High. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tE1LQV, t E2HQV, or t GLQV) rather than the address. Data out may be indeterminate at tE1LQX, tE2HQX and tGLQX, but data lines will always be valid at t AVQV (see Table 21, Figure 14, Figure 15). Write. Write operations are used to write data in the SRAM. The SRAM is in Write mode whenever the W and E1S pins are at VIL, with E2S at VIH. Either the Chip Enable inputs (E1S and E2S) or the Write Enable input (W) must be de-asserted during address transitions for subsequent write cycles. Write begins with the concurrence of both Chip Enables being active with W at VIL. A Write begins at the latest transition among E1S going to VIL, E2S going to VIH and W going to VIL. Therefore, address setup time is referenced to Write Enable and both Chip Enables as tAVWL, t AVE1L and tAVE2H respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the rising edge of E1S, the rising edge of W or the falling edge of E2S, whichever occurs first. If the Output is enabled (E1S=VIL, E2S=VIH and G=VIL), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVE1H before the rising edge of E1S or for tDVE2L before the falling edge of E2S, whichever occurs first, and remain valid for tWHDX, tE1HDX or tE2LDX (see Table 22, Figures 17, 18, 19). Output Disable. The data outputs are high impedance when the Output Enable (G) is at VIH with Write Enable (W) at VIH. Power-Down. The SRAM chip has a Chip Enable power-down feature which invokes an automatic standby mode (see Table 21, Figure 16) whenever either Chip Enable is de-asserted (E1S=V IH or E2S=VIL). Data Retention The SRAM data retention performances as VCCS go down to V DR are described in Table 23 and Figures 22, 23. In E1S controlled data retention mode, minimum standby current mode is entered when E1S VCCS - 0.2V and E2S 0.2V or E2S VCCS - 0.2V. In E2S controlled data retention mode, minimum standby current mode is entered when E2S 0.2V. Table 13. SRAM User Bus Operations (1) Operation Read Write Output Disable Power Down X Note: 1. X = VIL or VIH. E1S VIL VIL VIL VIH E2S VIH VIH VIH X VIL W VIH VIL VIH X X G VIL X VIH X X DQ0-DQ7 Data Output Data Input Hi-Z Hi-Z Hi-Z Power Active Active Active Stand-by TTL Stand-by TTL/CMOS 14/35 M36W108T, M36W108B Table 14. DC Characteristics (TA = 0 to 70C, -20 to 85C, -40 to 85C; VCCF = VCCS = 2.7V to 3.6V) Symbol ILI ILO ICCF1 ICCF2 (1) ICCF3 ICCS1 ICCS2 (1) ICCS3 VILF VIHF VILS VIHS VOLF VOHF VOLS VOHS Parameter Input Leakage Current Output Leakage Current Flash Chip Supply Current (Read) Flash Chip Supply Current (Write) Flash Chip Supply Current (Stand-by) SRAM Chip Supply Current (Read) SRAM Chip Supply Current (Write) SRAM Chip Supply Current (Stand-by) Flash Chip Input Low Voltage Flash Chip Input High Voltage SRAM Chip Input Low Voltage SRAM Chip Input High Voltage Flash Chip Output Low Voltage Flash Chip Output High Voltage SRAM Chip Output Low Voltage SRAM Chip Output High Voltage IOL = 1.8mA IOH = -100A IOL = 2.1mA IOH = -1.0mA 2.2 VCCF - 0.4 0.4 -0.5 0.7 VCCF -0.3 2.2 Test Condition 0V VIN VCCF / VCCS 0V VOUT VCCF / VCCS EF = VIL, G = VIH, f = 6MHz, V VOUT VCCF Program or Erase in progress EF = VCCF 0.2V E1S = VIL, E2S = VIH, f= 10MHz E1S = VIL, E2S = VIH, f= 1MHz Min -1 -1 Max 1 1 10 20 100 40 10 20 20 0.8 VCCF + 0.3 0.4 VCCS + 0.3 0.45 Unit A A mA A A mA mA mA A V V V V V V V V Note: 1. Sampled only, not 100% tested. Table 15. Capacitance (1) (TA = 25 C, f = 1 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF Note: 1. Sampled only, not 100% tested. Table 16. AC Measurement Conditions Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to 3V 1.5V Figure 5. AC Testing Load Circuit 0.8V 1N914 Figure 4. AC Testing Input/Output Waveforms DEVICE UNDER TEST 1.5V 0V AI01417 3.3k 3V OUT CL = 30pF or 100pF CL includes JIG capacitance AI01968 15/35 M36W108T, M36W108B Table 17. Flash Read AC Characteristics (TA = 0 to 70 C, -20 to 85 C or -40 to 85 C; VCCF = 2.7V to 3.6V) Flash Memory Chip 100 Symbol Alt Parameter Test Condition CL = 30pF Min tAVAV tAVQV tELQX (1) tELQV (2) tGLQX (1) tGLQV (2) tEHQX tEHQZ (1) tGHQX tGHQZ (1) tAXQX tPLYH (1,3) 120 Unit CL = 100pF Min 120 100 120 0 100 120 0 40 50 0 30 30 0 30 30 0 10 10 50 500 0 Max ns ns ns ns ns ns ns ns ns ns ns s ns ns ns Max tRC tACC tLZ tCE tOLZ tOE tOH tHZ tOH tDF tOH Address Valid to Next Address Valid Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enabled Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Transition to Output Transition EF = VIL, G = VIL EF = VIL, G = VIL G = VIL G = VIL EF = VIL EF = VIL G = VIL G = VIL EF = VIL EF = VIL EF = VIL, G = VIL 100 0 0 0 0 0 tRRB RP Low to Read Mode tREADY tRH tRP RP High to Chip Enable Low RP Pulse Width Chip Enabled Recovery Time 50 500 0 tPHEL tPLPX tCCR (4) Note: 1. 2. 3. 4. Sampled only, not 100% tested. G may be delayed by up to t ELQV - tGLQV after the falling edge of EF without increasing tELQV. To be considered only if the Reset pulse is given while the memory is in Erase, Erase Suspend or Program Mode. See Flash-SRAM Switching Waveforms. 16/35 tAVAV VALID tAVQV tELQV tAXQX Figure 6. Flash Read Mode AC Waveforms A0-A19 EF tEHQZ tELQX tEHQX G tGLQV tGLQX VALID tGHQX tGHQZ DQ0-DQ7 AI02511B M36W108T, M36W108B Note: Write Enable (W) = High. 17/35 M36W108T, M36W108B Table 18. Flash Write AC Characteristics, Write Enable Controlled (TA = 0 to 70 C, -20 to 85 C or -40 to 85 C; VCCF = 2.7V to 3.6V) Flash Memory Chip 100 Symbol Alt Parameter CL = 30pF Min tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tVCHEL tWHGL tPHPHH (1,2) tPLPX tWHRL (1) tPHWL (1) tVCS tOEH tVIDR tRP tBUSY tRSP tWC tCS tWP tDS tDH tCH tWPH tAS tAH Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low VCC High to Chip Enable Low Write Enable High to Output Enable Low RP Rise Time to VID RP Pulse Width Program Erase Valid to RB Delay RP High to Write Enable Low 4 100 0 50 50 0 0 30 0 50 0 50 0 500 500 90 4 Max CL = 100pF Min 120 0 50 50 0 0 30 0 50 0 50 0 500 500 90 Max ns ns ns ns ns ns ns ns ns ns s ns ns ns ns s 120 Unit Note: 1. Sampled only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. 18/35 M36W108T, M36W108B Figure 7. Flash Write AC Waveforms, W Controlled tAVAV A0-A19 VALID tWLAX tAVWL EF tELWL G tGHWL W tWHWL tDVWH DQ0-DQ7 VALID tWHDX tWLWH tWHGL tWHEH VCCF tVCHEL RB tWHRL AI02512 Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W. 19/35 M36W108T, M36W108B Table 19. Flash Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70 C, -20 to 85 C or -40 to 85 C; VCCF = 2.7V to 3.6V) Flash Memory Chip 100 Symbol Alt Parameter CL = 30pF Min tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tVCHWL tEHGL tPHPHH (1,2) tPLPX tEHRL (1) tPHWL (1) tVCS tOEH tVIDR tRP tBUSY tRSP tWC tWS tCP tDS tDH tWH tCPH tAS tAH Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low VCC High to Write Enable Low Chip Enable High to Output Enable Low RP Rise Time to VID RP Pulse Width Program Erase Valid to RB Delay RP High to Write Enable Low 4 100 0 50 50 0 0 30 0 50 0 50 0 500 500 90 4 Max CL = 100pF Min 120 0 50 50 0 0 20 0 50 0 50 0 500 500 90 Max ns ns ns ns ns ns ns ns ns ns s ns ns ns ns s 120 Unit Note: 1. Sampled only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. 20/35 M36W108T, M36W108B Figure 8. Flash Write AC Waveforms, EF Controlled tAVAV A0-A19 VALID tELAX tAVEL W tWLEL G tGHEL EF tEHEL tDVEH DQ0-DQ7 VALID tEHDX tELEH tEHGL tEHWH VCCF tVCHWL RB tEHRL AI02513 Note: Address are latched on the falling edge of EF, Data is latched on the rising edge of EF. Figure 9. Flash Read and Write AC Waveforms, RP Related EF tPHEL W tPHWL RB RP tPLPX tPHPHH tPLYH AI02514 21/35 M36W108T, M36W108B Table 20. Flash Data Polling and Toggle Bits AC Characteristics (1) (TA = 0 to 70 C, -20 to 85 C or -40 to 85 C; VCCF = 2.7V to 3.6V) Flash Memory Chip 100 Symbol Parameter CL = 30pF Min Write Enable High to DQ7 Valid (Program, W Controlled) tWHQ7V Write Enable High to DQ7 Valid (Chip Erase, W Controlled) Chip Enable High to DQ7 Valid (Program, EF Controlled) tEHQ7V Chip Enable High to DQ7 Valid (Chip Erase, EF Controlled) Q7 Valid to Output Valid (Data Polling) Write Enable High to Output Valid (Program) tWHQV Write Enable High to Output Valid (Chip Erase) Chip Enable High to Output Valid (Program) tEHQV Chip Enable High to Output Valid (Chip Erase) 10 1.0 10 1.0 10 1.0 10 1.0 Max 2400 60 2400 60 40 2400 60 2400 60 10 1.0 10 1.0 CL = 100pF Min 10 1.0 10 1.0 Max 2400 60 2400 60 50 2400 60 2400 60 ms sec s sec ns s sec s sec 120 Unit tQ7VQV Note: 1. All other timings are defined in Read AC Characteristics table. 22/35 A0-A19 ADDRESS (WITHIN BLOCKS) tAVQV tELQV EF tEHQ7V G tGLQV Figure 10. Flash Data Polling DQ7 AC Waveforms W tWHQ7V DQ7 VALID DQ7 DQ0-DQ6 IGNORE tQ7VQV VALID DATA POLLING READ CYCLES DATA POLLING (LAST) CYCLE MEMORY ARRAY READ CYCLE AI02515B LAST WRITE CYCLE OF PROGRAM OR ERASE INSTRUCTION M36W108T, M36W108B 23/35 24/35 VALID tEHQV tAVQV tELQV tGLQV tWHQV STOP TOGGLE VALID IGNORE VALID DATA TOGGLE READ CYCLE DATA TOGGLE READ CYCLE MEMORY ARRAY READ CYCLE AI02516 M36W108T, M36W108B A0-A19 EF G Figure 11. Flash Data Toggle DQ6, DQ2 AC Waveforms W DQ6,DQ2 DQ0-DQ1,DQ3-DQ5,DQ7 LAST WRITE CYCLE OF PROGRAM OF ERASE INSTRUCTION Note: All other timings are as a normal Read cycle. M36W108T, M36W108B Figure 12. Flash Data Polling Flowchart Figure 13. Flash Data Toggle Flowchart START START READ DQ5 & DQ7 at VALID ADDRESS READ DQ2, DQ5 & DQ6 DQ7 = DATA NO NO YES DQ2, DQ6 = TOGGLE YES NO NO DQ5 =1 YES READ DQ7 DQ5 =1 YES READ DQ2, DQ6 DQ7 = DATA NO FAIL YES DQ2, DQ6 = TOGGLE YES PASS FAIL NO PASS AI01369 AI01873 25/35 M36W108T, M36W108B Table 21. SRAM Read AC Characteristics (TA = 0 to 70 C, -20 to 85 C or -40 to 85 C; VCCS = 2.7 V to 3.6 V) SRAM Chip 100 Symbol Parameter CL = 100pF Min tAVAV tAVQV tE1LQV tE2HQV tGLQV tE1LQX tE2HQX tGLQX tE1HQZ tE2LQZ tGHQZ tAXQX tPU (1) tPD (1) tCCR (2) Read Cycle Time Address Valid to Output Valid Chip Enable 1 Low to Output Valid Chip Enable 2 High to Output Valid Output Enable Low to Output Valid Chip Enable 1 Low to Output Transition Chip Enable 2 High to Output Transition Output Enable Low to Output Transition Chip Enable 1 High to Output Hi-Z Chip Enable 2 Low to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition Chip Enable 1 Low or Chip Enable 2 High to Power Up Chip Enable 1 High or Chip Enable 2 Low to Power Down Chip Enable Recovery Time 0 10 10 5 0 0 0 15 0 100 30 30 30 100 100 100 100 50 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. Sampled only. Not 100% tested. 2. See Flash-SRAM Switching Waveforms. Figure 14. SRAM Read Mode AC Waveforms, Address Controlled tAVAV A0-A16 tAVQV tAXQX VALID DQ0-DQ7 DATA VALID DATA VALID AI02436 Note: E1S = Low, E2S = High, G = Low, W = High. 26/35 M36W108T, M36W108B Figure 15. SRAM Read AC Waveforms, E1S, E2S or G Controlled tAVAV A0-A16 tAVQV tE1LQV E1S tE1LQX tE2HQV E2S tE2HQX tGLQV G tGLQX DQ0-DQ7 DATA VALID AI02435 VALID tAXQX tE1HQZ tE2LQZ tGHQZ Note: Write Enable (W) = High. Figure 16. SRAM Stand-by AC Waveforms E1S E2S ICC4 ICC5 tPU 50% tPD AI02517 27/35 M36W108T, M36W108B Table 22. SRAM Write AC Characteristics (TA = 0 to 70 C, -20 to 85 C or -40 to 85 C; VCCS = 2.7 V to 3.6 V) SRAM Chip 100 Symbol Parameter CL = 100pF Min tAVAV tAVWL tAVWH tWLWH tWHAX tWHDX tWHQX tWLQZ tAVE1L tAVE2H tE1HAX tE2LAX tDVWH tDVE1H tDVE2L Write Cycle Time Address Valid to Write Enable Low Address Valid to Write Enable High Write Enable Pulse Width Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to Output Hi-Z Address Valid to Chip Enable 1 Low Address Valid to Chip Enable 2 High Chip Enable 1 High to Address Transition Chip Enable 2 Low to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable 1 High Input Valid to Chip Enable 2 Low 100 0 80 70 0 0 0 0 0 0 0 0 40 40 40 30 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Figure 17. SRAM Write AC Waveforms, W Controlled tAVAV A0-A16 VALID tAVWH tAVE1L E1S tAVE2H E2S tAVWL W tWLQZ tDVWH DQ0-DQ7 INPUT VALID AI02434 tWHAX tWLWH tWHQX tWHDX Note: Output Enable (G) = Low. 28/35 M36W108T, M36W108B Figure 18. SRAM Write AC Waveforms, E1S Controlled tAVAV A0-A16 tAVE1L E1S VALID tE1HAX E2S tAVWL W tDVE1H DQ0-DQ7 INPUT VALID tWHDX AI02433 Note: Output Enable (G) = High. Figure 19. SRAM Write AC Waveforms, E2S Controlled tAVAV A0-A16 VALID E1S tAVE2H E2S tAVWL W tDVE2L DQ0-DQ7 INPUT VALID tWHDX tE2LAX AI02432 Note: Output Enable (G) = High. 29/35 M36W108T, M36W108B Table 23. SRAM Low VCC Data Retention Characteristics (1, 2) (TA = 0 to 70 C; VCCS = 2.7 V to 3.6 V) Symbol ICCDR VDR tCDR tR Parameter Supply Current (Data Retention) Supply Voltage (Data Retention) Chip Disable to Power Down Operation Recovery Time Test Condition VCCS = 3V, E1S VCCS - 0.2V, E2S VCCS - 0.2V or E2S 0.2V, f = 0 E1S VCCS - 0.2V,E2S 0.2V, f = 0 E1S VCCS - 0.2V,E2S 0.2V, f = 0 2 0 5 Min Max 20 3.6 Unit A V ns ms Note: 1. All other Inputs VIH VCC - 0.2V or VIL 0.2V. 2. Sampled only. Not 100% tested. Figure 20. SRAM Low VCC Data Retention AC Waveforms, E1S Controlled tCDR VCCS 2.7 V 2.2 V VDR DATA RETENTION MODE tR E1S VCCS - 0.2V E1S V SS AI02438 30/35 M36W108T, M36W108B Figure 21. SRAM Low VCC Data Retention AC Waveforms, E2S Controlled DATA RETENTION MODE VCCS 2.7 V E2S tCDR VDR 0.4 V VSS AI02437 tR E2S 0.2V Figure 22. Flash-SRAM Switching Waveforms EF tCCR E1S tCCR E2S AI02510 31/35 M36W108T, M36W108B Table 24. Ordering Information Scheme Example: Product Family M36 = MMP (Flash + SRAM) Operating Voltage W = 2.7V to 3.6V SRAM Chip size & organization 1 = 1 Mbit (128Kb x8) Flash Chip size & orgnization 08 = 8 Mbit (1Mb x8), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 100 = 100 ns 120 = 120 ns Package ZM = LBGA48: 1mm pitch ZN = LGA48: 1mm pitch Temperature Range 1 = 0 to 70 C 5 = -20 to 85 C 6 = -40 to 85 C Option T = Tape & Reel Packing M36W108T 100 ZM 1 T The M36W108T and M36W108B are replaced respectively by the new version M36W108AT and M36W108AB. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 32/35 M36W108T, M36W108B Table 25. LBGA48 - 6 x 8 balls, 1.0 mm pitch, Package Mechanical Data mm Symb Typ A A1 A2 b ddd D D1 e E E1 SD SE 10.000 5.000 1.000 12.000 7.000 0.500 0.500 9.800 - - 11.800 - - - 1.250 0.300 0.950 0.400 Min 1.150 0.250 - 0.350 Max 1.350 0.350 - 0.450 0.150 10.200 - - 12.200 - - - 0.394 0.197 0.039 0.472 0.276 0.020 0.020 0.386 - - 0.465 - - - Typ 0.049 0.012 0.037 0.016 Min 0.045 0.010 - 0.014 Max 0.053 0.014 - 0.018 0.006 0.402 - - 0.480 - - - inches Figure 23. LBGA48 - 6 x 8 balls, 1.0 mm pitch, Package Outline D D1 SD BALL "A1" E E1 SE ddd e A b A2 A1 BGA-Z01 Drawing is not to scale. 33/35 M36W108T, M36W108B Table 26. LGA48 - 6 x 8 balls, 1.0 mm pitch, Package Mechanical Data mm Symb Typ A b D D1 D2 e E E1 E2 SD SE 0.950 0.450 10.000 5.000 9.200 1.000 12.000 7.000 10.200 0.500 0.500 Min 0.900 0.420 9.800 - - - 11.800 - - - - Max 1.000 0.480 10.200 - - - 12.200 - - - - Typ 0.037 0.018 0.394 0.197 0.362 0.039 0.472 0.276 0.402 0.020 0.020 Min 0.035 0.017 0.386 - - - 0.465 - - - - Max 0.039 0.019 0.402 - - - 0.480 - - - - inches Figure 24. LGA48 - 6 x 8 balls, 1.0 mm pitch, Package Outline D D2 D1 SD LAND "A1" E E2 E1 SE e b A LGA-Z02 Drawing is not to scale. 34/35 M36W108T, M36W108B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics (R) 1999 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 35/35 |
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